GE-Switch
A custom-built network switch design for linking multiple AI processors (like Ascend NPUs and Nvidia Xavier chips) into one compact distributed computing system.
GE-Switch Explanation
This project is a custom-built network switch designed to connect multiple AI processors together into a single distributed computing system. Instead of buying an off-the-shelf switch, the creator is designing one from scratch—partly for the engineering challenge, partly because they want something compact and tailored to their specific needs.
Here's what it's for: the creator is building a mobile AI processing center using high-performance chips (potentially Ascend NPUs and Nvidia Xavier processors). These chips need to talk to each other quickly and reliably to share AI inference tasks. Rather than connecting them through a standard commercial switch, they're using a GE (Gigabit Ethernet) network and building a custom switch to manage that traffic. The switch acts as the central hub that lets all the AI nodes communicate.
The project is in early stages. The circuit schematics are mostly done, but the physical layout (the detailed design of how components fit on the board) is still being worked out. The creator opened this repository to document their progress and hold space for the design files they'll eventually publish. If you're interested in hardware design, networking, or building custom infrastructure for AI workloads, this shows one person's approach to solving a specific engineering problem by designing rather than buying.
The note at the end is a bit self-aware: the creator acknowledges this is partly driven by a personal preference for compact, efficient hardware design. Rather than accept the size and design tradeoffs of commercial switches, they're building exactly what they need.
Where it fits
- Connect multiple AI accelerator chips like Ascend NPUs and Nvidia Xavier into one distributed compute node.
- Design a compact custom network switch instead of using a bulky off-the-shelf one.
- Build a mobile AI processing center that needs fast, reliable inter-chip communication.
- Study one engineer's approach to custom hardware design for AI infrastructure.